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OVMS hardware version 4 - move on to RISC-V

I have read some hours through the history of the project on the mailing list and some other sources on the web. The version number of the OVMS represent the CPU architecture. There was a user some years ago before hardware revision 3.3 was released. This user named for himself the hardware he build OVMS version 4. The reason why the user decide this was the "4G" modem the OVMS 3 up to 3.2 did not had. He probably expected OVMS 3 to be "3G". One of the core developer and the admin of this forum Mark explained the user that this version number does not represent the modem network version. It represent the CPU architecture.

RISC-V is since many years the only and most free CPU architecture out there. The RISC-V cpu architecture have its own developer rooms on free and open source conferences like https://fosdem.org/2024/schedule/track/risc-v-devroom/ . RISC-V is not used at the moment by OVMS. OVMS v3 use the Xtensa LX6 architecture and the ESP-IDF. It also need based on information the developer Dexter provide at least 4MB of RAM to run. At the moment now there is no practical RISC-V solution to not have to reinvent the wheel to move to RISC-V. But beginning with the next month (April 2024) there would be. Its the ESP32-P4. Its faster, modern and support RISC-V with PSRAM. The current ESP32-C2,C3 and C6 (the current RISC-V SoC's released by espressif) does not support PSRAM and thus are not usable for OVMS with their <1MB of build in RAM.

The ESP32-P4 have also many other benefits like capability of real cable network, real USB (the ESP32-S3 also have real USB and PSRAM, but OVMS hardware never switched to ESP32-S3 with its Xtensa LX7) and much more. Many products based on the ESP32-P4 would also be combined with WiFi6, 802.15.4 and much other interesting things.


I dont know if the OVMS developer have already now too much CPU power for the things they do with the current ESP32 code. If this is the case, then all the named modern benefits with PSRAM can also be got with the ESP32-C61 that is single core but would be released widely at Q3 or Q4 2024.


Of course the ESP-IDF have to be updated from the current and fully outdated (security issues exist and are not fixed and would never be fixed) version 3.3 to recent one. The ESP-IDF version 5.3 would fully support the ESP32-P4. The ESP-IDF 5.4 would start supporting the ESP32-C61.


Having OVMSv4 with RISC-V (32bit) ESP32 hardware like ESP32-P4 or ESP32-C61 would be great. OVMSv4.1 could be then the 5G-modem version laugh


Maybe in many many years OVMSv5 could be then the RISC-V 64bit SoC version with WiFi 8, 6G-modem and Micro-SD NVMe slot cheeky

markwj's picture
The ESP32-P4 has no wifi. I

The ESP32-P4 has no wifi. I prefer the ESP32-S3 as a more logical upgrade path.

The upcoming ESP32-P4 boards

The upcoming ESP32-P4 boards would have wifi. There are rumors about getting a combined ESP32-P4 with a ESP32-C6.

Quote a reddit user that posted this 3 days ago:


the ESP32-P4 will come with a ESP32-C6 as a Wifi Companion Chip.

The Solution is "Esp-hosted", they are working intensively in the Repo.

so this will be a very powerful Combination.

you can make 5 CAN Channels then (3 on the P4, 2 on the C6) ...


Here are more ESP32 CAN related posts from this user: https://www.reddit.com/user/PageExtreme9327/


Interesting for example could be this post:

ESP32-C6 has 2 CAN-Bus.

ESP32 or ESP32S3 you can use CAN-SPI Chips to add a second CAN Channel.

but cheaper than such a chip is to tie 2 ESP32 together: you have also more Can Channels.


If some time is been spend into redoing parts of the board with a new SoC, i would vote for spending this time in RISC-V. RISC-V in general is also better protected from sanctions we see more and more.

If you disable one of the two CPU's of a ESP32 and even downclock it, does this create some issues running OVMS? Asking this because of the ESP32-C61 that is cheap in production.


Could a P4 combined with a C6 remove the need of the MAX7317AEE ? And when you have then 5 times CAN provided by the P4+C6, you maybe also dont need the MCP2515 any more?


Tesla people are to what i read the ones who want more then 3 CAN interfaces in OVMS. They then add a forth one to connect to everything. When having 5 by using a board with P4+C6, you would also fit their needs.

markwj's picture
Using multiple

Using multiple microprocessors on a project this size seems the wrong direction. Complexity, power consumption, etc. Even having two flash images and having to somehow flash the second MCU from the first is a PITA.

I like the P4 chip, but can only wish Espressif will release one with wifi and bluetooth onboard (as well as more SRAM or at least the ability to work around IRAM restrictions). GPIO and IRAM are our main hurt points. Extra CAN buses are easy (via SPI), relatively low power, and can be turned off if not needed.

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